As is well known, liquid crystal display devices have been used in large numbers as the screen display devices for computer devices, for example. In coming years, the liquid crystal display device is expected to expand its range of TV applications. However, a TN (Twisted Nematic) mode, which is currently in wide use, has major display performance problems for use in a TV, such as a narrow viewing angle, an unsatisfactory response time, reduced contrast due to parallax, and blurring of a moving image.
In recent years, the studies on an OCB mode have been advanced in place of the aforementioned TN mode. The OCB has characteristics which provide for a wider viewing angle and a faster response compared to that of TN, and thus it can be said that the OCB is a display mode more suitable for displaying natural moving images.
A conventional liquid crystal display device is described below.
In a display region of a liquid crystal display device, as shown in FIG. 16, source lines 1601 (S1, S2, . . . ), gate lines 1602 (G1, G2, . . . ), and thin film transistors (hereinafter referred to as “TFTs”) 1603, serving as switching elements, are provided. A drain electrode of each TFT is connected to a pixel electrode in a pixel 1604. Each pixel 1604 comprises a pixel electrode, a counter electrode, and liquid crystal sandwiched and held between those electrodes. A stray capacitance 1606 is present between the pixel electrode and the source line 1601. For example, the stray capacitance between a source line S2 and a pixel on the left side of the source line S2 is indicated as C2L and the stray capacitance between the source line S2 and a pixel on the right side of the source line S2 is indicated as C2R.
The counter electrode of each pixel 1604 is connected to a counter drive line 1605 and is driven by a counter voltage Vcom.
Next, with reference to FIG. 17, the configuration related to the driving of a conventional liquid crystal display device is described. This conventional liquid crystal display device comprises a signal conversion part 1701, a source driver 1703, a gate driver 1704, a drive pulse generation part 1702 for generating a pulse used for driving each driver, and a display region part 1705 of a liquid crystal panel whose configuration is illustrated in the aforementioned FIG. 16. The signal conversion part 1701 increases the speed of an input image signal by R times at every one horizontal period, R being obtained from R=(N+1)/N, where N is an integer equal to or greater than 1, and converts it to a display signal, which is the image signal whose speed has been increased by R times, and a non-display signal with an R-times speed.
From the signal conversion part 1701, the display signal and the non-display signal are sent to the source driver 1703. The source driver 1703 converts, in accordance with the control of a source driver control signal sent from the drive pulse generation part 1702, the polarity and voltage of the display and non-display signals to an appropriate polarity and voltage for each pixel, and then outputs them as a display signal voltage and a non-display signal voltage.
A multiplexer part 1706 is disposed between the source driver 1703 and the display region part 1705. The multiplexer part 1706 selectively supplies, under the control of a multiplexer control signal sent from the drive pulse generation part 1702, to a plurality of source lines 1601 the display signal voltage and the non-display signal voltage outputted from the source driver 1703 by switching between the source lines in a time-sharing manner.
The gate driver 1704 supplies, in accordance with the control of a gate driver control signal sent from the drive pulse generation part 1702, an ON or OFF potential of the TFT 1603 on the gate line 1602 in synchronization with the output of the display signal voltage or non-display signal voltage from the source driver 1703.
A power supply part 1707 supplies a voltage having a desired polarity and voltage value to each function block in the manner indicated by the dotted lines.
The voltage that is applied to both ends of a liquid crystal cell, such as the pixel 1604 in the display region part 1705, is a difference between the voltage Vcom to be supplied to the counter electrode and the aforementioned display signal voltage or non-display signal voltage to be applied to each pixel 1604 via the source line 1601 and the TFT 1603, and this determines the transmittance of each pixel 1604.
Furthermore, the polarity of the voltage to be applied to both ends of a liquid crystal cell is defined based on whether the difference between the above-described voltage Vcom and the above-described display signal voltage or non-display signal voltage to be applied to each pixel 1604 is positive or negative, and thus is not simply defined by the voltage polarity of the above-described display signal voltage or non-display signal voltage. However, in the following description, for simplicity of description, the polarity of the voltage applied to both ends of a liquid crystal cell will be referred to as the polarity of the above-described display signal voltage or non-display signal voltage.
Such a driving method is similarly employed in both an OCB cell and a TN-type cell. The OCB cell, however, requires a unique driving, which is not required for the TN-type cell, at a start-up stage where an image display is started. The OCB cell has a bend alignment with which an image display can be performed, and a splay alignment with which an image display cannot be performed. To shift from a splay alignment to a bend alignment (hereinafter referred to as a “transition”), a unique driving is required, such as a high-voltage application for a certain time. Note that the driving related to this transition is not directly related to the present invention, and thus any further description is not provided herein.
The OCB cell has a problem in that even if a bend-alignment transition is obtained once by the aforementioned unique driving, if a voltage with a predetermined level or greater is not applied for at least a certain time, the bend alignment cannot be maintained, resulting in a return to a splay alignment (this phenomenon is hereinafter called a “reverse transition”).
To suppress the occurrence of a reverse transition, it is known that a high voltage may be applied periodically, as described in Japanese Laid-Open Patent Publication No. 11-109921 and Journal of the Japanese Liquid Crystal Society (Nihon Ekisho Gakkaishi), Apr. 25, 1999 (Vol. 3. No. 2), pp. 99(17)–106(24). This high potential corresponds to the above-described non-display signal voltage. By periodically applying this non-display signal voltage by the driving, as will be described later, the occurrence of a reverse transition can be suppressed. It is common practice to use the maximum voltage of the above-described display signal voltage, which corresponds to a black display, as this non-display signal voltage in view of the effect of suppressing the occurrence of a reverse transition and the display quality. The driving that a high potential is periodically applied to suppress a reverse transition is hereinafter called “CR (Cyclic Resetting) driving”.
Typical potential-transmittance curves for OCB are illustrated in FIG. 18.
In FIG. 18, a curve 1801 is a potential-transmittance curve in the case where a predetermined potential for preventing a reverse transition is not inserted, and a curve 1802 is a potential-transmittance curve in the case of CR driving where a predetermined potential for preventing a reverse transition is inserted. A potential 1803 is a critical potential Vth at which a reverse transition from a bend alignment to a splay alignment occurs in the case where a reverse transition is not prevented. A potential 1804 is a potential (white potential) when the transmittance is maximum, and a potential 1805 is a potential (black potential) when the transmittance is minimum. In the case where a reverse transition is not prevented, if the potential is Vth or lower, the alignment returns to a splay alignment, and thus an appropriate transmittance cannot be obtained. Therefore, driving with a potential of Vth or higher is required. In this case, however, as shown in the figure, the transmittance that corresponds to the potential 1803 is the maximum transmittance, and therefore a sufficient luminance cannot be obtained.
Liquid crystals represented by OCB and TN require so-called alternating-current driving. However, any specific configuration of such driving is not described in either the aforementioned Japanese Laid-Open Patent Publication No. 11-109921 or Journal of the Japanese Liquid Crystal Society, and thus what sort of alternating-current reversal should be performed cannot be identified from these references. Hence, as a conventional example, the CR driving performed by a combination of a line-by-line reversal and a frame-by-frame reversal, which is the most typical driving in a liquid crystal display device, is described with reference to FIGS. 19, 20, and 22.
FIG. 19 shows the configuration of the source driver 1703, the display region part 1705, and the multiplexer part 1706 of a conventional liquid crystal display device, shown in the aforementioned FIG. 17. Note that a group of source lines is indicated as “1901” and a group of gate lines is indicated as “1902”.
For simplicity, FIG. 19 shows a portion that corresponds to the upper left portion of the multiplexer part 1706, including four source lines and eight gate lines, two outputs indicated by ST1 and ST2 as the output terminals of the source driver 1703, and switching elements in the multiplexer part 1706 only for the four source lines. For the remainder, the same configuration as above is repeated, and thus the illustration thereof is omitted.
As for the display region part 1705, “R”, “G”, and “B” shown in the pixels indicate color attributes of the pixels, the ensuing number indicates the row number (i.e., the row number of the gate lines) in the display region, and “+” or “−” indicates the voltage polarity that the liquid crystal cell holds in a given one screen.
Reference numeral 1903 indicate multiplexer control signals denoted as CTL0 and CTL1 respectively, and each signal is connected to the gate of each switching element in the multiplexer part 1706, as shown in the figure. The switching element in the multiplexer part 1706 is indicated by a two-digit number following “MP”, and the first digit indicates the control signal number and the second digit indicates the number of the source line to which the switching element is connected. In addition, the source and drain of each switching element in the multiplexer part 1706 are connected to the source driver 1703 and a source line, respectively. Each of the outputs ST1 and ST2 of the source driver 1703 is divided in two, and is connected to adjacent source lines via the multiplexer part 1706.
FIG. 20 is a timing diagram illustrating the control performed by a conventional liquid crystal display device. Here, an exemplary operation in the case where N=4 is described. In the figure, SP1 and SP2 are a type of a source driver control signal and are control signals for controlling the polarity of the output voltage of the source driver 1703. In the HIGH period of SP1, the aforementioned display signal voltage or non-display signal voltage, in which ST1 has a positive polarity and ST2 has a negative polarity, is outputted. In the LOW period, a display signal voltage or non-display signal voltage, in which ST1 has a negative polarity and ST2 has a positive polarity, is outputted. SQ1 and SQ2 indicate the type and polarity of the output voltages of ST1 and ST2 of the source driver 1703 which are respectively controlled by the aforementioned SP1 and SP2. Here, “K” indicates the aforementioned non-display signal voltage, “R”, “G”, and “B” indicate the aforementioned display signal voltages each having a display color attribute, and “+” and “−” indicate the polarity of each voltage. The non-display signal voltage, indicated by “K”, indicates the output voltage of the source driver 1703 with respect to a non-image signal that is inserted in the display signal voltage at a rate conversion of R=5/4=1.25 times speed in the signal conversion part 1701.
The “SWP” is another type of a source driver control signal, and is a signal for controlling the output timing of the source driver 1703. By the rise and fall of the SWP's HIGH and LOW logic (indicated by arrows in the figure), the source driver begins to produce an output.
In the HIGH period of CTL0, the switching elements MP10 and MP40 in the multiplexer part 1706 connected to the source lines S1 and S4, respectively, are electrically conducted, and consequently the output of ST1 is supplied to S1 and the output of ST2 is supplied to S4. Then, in the LOW period of CTL0, these supplies are interrupted. Similarly, in the HIGH period of CTL1, the switching elements MP21 and MP31 in the multiplexer part 1706 connected to the source lines S2 and S3, respectively, are electrically conducted, and consequently the output of ST1 is supplied to S2 and the output of ST2 is supplied to S3. Then, in the LOW period of CTL1, these supplies are interrupted.
S1P, S2P, etc., indicate the states of the potentials of the source lines, such as S1 and S2, resulting from the application of the aforementioned display signal voltage and non-display signal voltage to the source lines by the above-described signal voltage control. The symbols “K”, “R”, “G”, “B”, “+” and “−” mean the same as those described for SQ1 and SQ2. Note that the number following “K”, “R”, “G”, or “B” indicates the row number of the gate lines.
T01 to T10 indicate one period (one cycle) of R-times speed driving in the case where N=4. When one horizontal period of an input image signal is indicated as 1H, the length of each period is equivalent to NH/(N+1), and 10 cycles are equivalent to 8H.
As for the flow of a signal voltage, for example, the non-display signal voltage of K+ of SQ1 present in the former part of the T01 period is outputted at the time of the rise of SWP at the beginning of this period, and then applied to the electric capacitances (all capacitances belonging to S1, such as, for example, the TFT 1603 and the stray capacitance 1606) of the source line S1 via the switching element MP10 in the multiplexer part 1706 which is electrically conducted while CTL0 is HIGH, whereby S1P takes a non-display signal voltage of the symbol “K+”. In the latter part of T01, CTL0 becomes LOW and thus the switching element MP10 in the multiplexer part 1706 on the source line S1 is interrupted, whereby the non-display signal voltage of K+ remains on the source line S1 until the end of the T01 period. In the subsequent former part of the T02 period, the display signal voltage of R+ of SQ1 is applied to the source line S1 in a similar process, and the display signal voltage of R+ remains on the source line S1 until the end of the T02 period. Concurrently, during the period from the latter part of T01 to the former part of T03, the non-display signal voltage of K− on SQ1 and the subsequent display signal voltage of G− are each outputted at the time of the fall of SWP and applied to the source line S2, whereby these voltages each remain on the source line S2 for a predetermined period. Following this, the potential changes in the source lines S1 and S2 are repeated in a similar process for one cycle starting T01 and ending T10. The states of SQ2, S3P, and S4P are similar to the above.
The group of gate lines 1902, shown in FIG. 19, is driven by gate-line drive pulses which are generated by the gate driver 1704 upon receipt of gate driver control signals from the drive pulse generation part 1702. That is, the gate line drive pulses G1P, G2P, . . . , such as those shown in FIG. 21, are applied to the gate lines G1, G2, . . . , respectively. In the period when the ON potential of, for example, the pixel TFT 1603 is exceeded (e.g., the period of TKW and the subsequent high-potential period, shown in FIG. 21), the TFT 1603 of a corresponding pixel 1604 turns to an ON state, and the charging of the source line potential, shown in FIG. 20, (hereinafter referred to as “writing”) is performed on the liquid crystal cell.
Here, an example of conventional driving is such that four gate lines G1 to G4 are simultaneously selected in the aforementioned TKW period (i.e., the period which lies 2KNH before T01, shown in FIG. 20, where K is a positive integer and N is 4 in this example), and a non-display signal voltage is written to all pixels on the gate lines G1 to G4. Further, in the time within 4H after a predetermined period {(2K−1)NH}, the display signal voltages of R, G, and B are sequentially written to the pixel cells on each of the gate lines G1 to G4. The subsequent four gate lines G5 to G8 repeat a similar operation after a 4H delay from the gate lines G1 to G4. At this point, the polarity of the potential of the source line is reversed, as shown in FIG. 20. This operation is performed over all gate lines and completed in one frame. As described above, all gate lines in the display region part 1705 are selected twice in one frame period, and a display signal voltage and a non-display signal voltage are each written to the pixels on each gate line once.
In the subsequent frame, in order to reverse the polarity of the pixel voltage, the phases of SP1 and SP2 are shifted 180 degrees. This is the CR driving method, described as a conventional example, which employs a one-column reversal, a four-line reversal, and a frame reversal.
For the control and output operation methods of the source driver, many known modes are available, but such methods are not directly related to the present invention. The same is true of the settings of the aforementioned TKW and the invariable K, which are gate drive conditions, and the setting of N for an R-times speed, a detailed operation, etc. Therefore, any further description thereof is not provided herein.
The display signal voltage and non-display signal voltage can be periodically written by the above-described operation. By appropriately providing the voltage of this non-display signal voltage, a reverse transition of an OCB liquid crystal cell can be prevented.
The above-described driving, however, is associated with the following problems resulting from the fact that the time the non-display signal voltage is applied to the source line from the source driver 1703 is split into the former and latter parts in each period of T01 or T06, or a period which exists 2KNH therebefore or thereafter, and resulting from the open state of the source line occurred during the interruption period of the multiplexer part 1706. The problems are described below with reference to FIGS. 22 and 23.
(a) of FIG. 22 illustrates the transitional state of the potential changes in source lines. The symbols shown in the figure. are the same as those shown in FIG. 20. For example, looking at SQ1, S1P, and S2P in the period T01, when K+ on SQ1 is applied to the source line S1 in the former part of T01, a potential change occurs in S1P in the forward direction (in the figure, the potential change in the forward direction is indicated by an upward arrow).
When K− on SQ1 is applied to the source line S2 in the latter part of T01, a potential change occurs in S2P in the reverse direction (in the figure, the potential change in the reverse direction is indicated by a downward arrow). In the period T06, those potential changes occur in the opposite directions to the above. Similar potential changes occur in SQ2, S3P, and S4P. In practice, even in other periods, potential changes occur resulting from the application of the display signal voltages of R, G, and B to each source line. However, as described above, the voltage value of the display signal voltage is equal to or lower than that of the non-display signal voltage, and changes in a slight degree in accordance with the content of a pixel signal, and thus the influence of such changes is small. Therefore, for simplicity of description, such an influence is not taken into consideration here.
Adjacent source lines are electrically coupled to each other by capacitances connected in series with each other with a TFT drain electrode disposed therebetween, such as, for example, a pair of C1R and C2L and a pair of C2R and C3L, shown in FIG. 16. In addition, each pixel is electrically coupled, by these stray capacitances, to source lines present on both sides of the pixel.
Therefore, the potential change in a source line may possibly exert a comparatively great influence on pixels present on the sides of the source line or on source lines present on the sides of the source line.
The OFF pixel in (b) of FIG. 22 is a pixel to which a display signal voltage or a non-display signal voltage has been written, but the subsequent display signal voltage or non-display signal voltage has not been written. In other words, the OFF pixel is a pixel in which the TFT 1603 is in an OFF state.
As shown in (b1) of FIG. 22, the change of K− in S2P in the latter part of T01 exerts as influence in the reverse direction on all OFF pixels present between the source lines S1 and S2.
In the figure, this is indicated as “influence on OFF pixels”, and the polarity of such an influence is indicated by an arrow. In addition, in this period, the source line S1 is in an open state with respect to the multiplexer part 1706. Therefore, the source line S1 which is in an open state in this period receives a similar influence in the reverse direction from the aforementioned OFF pixel. In the figure, this is indicated as “influence on potentials of former open source lines”, and the polarity of such an influence is indicated by an arrow. Similarly, the change of K+ in S3P in the latter part of T01 exerts the influence in the forward direction on all OFF pixels present between the source lines S3 and S4, and also exerts the influence in the forward direction on the source line S4 which is in an open state in this period. As for the OFF pixels present between the source lines S2 and S3, because S2P and S3P cause changes in directions opposite to each other, these influences counteract each other, and thus if C2R≈C3L, the influences on these OFF pixels are small. In the figure, a small influence on the OFF pixel is indicated by a black square. As for the OFF pixels present between the source lines S4 and S5, because there are no changes in S4P and S5P, no influence is exerted on the OFF pixels, and thus no particular symbol is provided in the figure.
Although the changes which occurred in the source lines S1 and S4 are superimposed on the write voltages of display signal voltages in the subsequent periods T02 to T05, their polarities are opposite to that of the display signal voltages written thereto, and thus the degree of the influence is evaluated as “−1” and the evaluation rating is provided in (b1) of FIG. 22.
The change of K+ in S1P and the change of K− in S4P in the former part of T01 exert an influence on the source lines S2 and S3 which are in an open state in this period, but immediately after this, the non-display signal voltages of K− and K+ are supplied to the source lines S2 and S3, and therefore such an influence is eliminated at this point and no influence is exerted on the writing of a display signal voltage in any period after T02. Thus, the evaluation ratings to the source lines S2 and S3 in (b1) of FIG. 22 result in “0”.
The pixels to which a display signal voltage have been written in T02 remain as OFF pixels after T03 until a non-display signal voltage is written in the next frame. The influence exerted on these pixels from source lines in the meantime is discussed now. Note that such an influence is a repetition of the influence of the periods D to F, shown in FIG. 22, and therefore the degree of the influence is evaluated in these periods.
(b2) of FIG. 22 schematically illustrates the changes in the source lines S1 to S4 caused by the non-display signal voltage during the periods D to F. As shown in the figure, no influence is exerted on the OFF pixels on average during these periods, and thus the evaluation ratings to the source lines S1 to S4 result in “0”.
The influence on the pixels for one frame resulting from the writing of a non-display signal voltage is expressed as a sum of the evaluation ratings indicated in (b1) of FIG. 22 and (b2) of FIG. 22. That is, as shown in (b3) of FIG. 22, it can be seen that in the pixels on a source line Sj, which corresponds to j=4i−3 or j=4i, where i=1, 2, 3 . . . , the transmittance becomes higher than the originally intended value (i.e., the luminance is increased). FIG. 23 is a schematic diagram illustrating display images. (a) of FIG. 23 shows the example where the pixels of R, G, and B are operated at an original constant luminance. In this case, an image is obtained which has no display non-uniformity when viewed from an appropriate visual distance, such as that shown in (b) of FIG. 23. In the aforementioned conventional example, however, as the result of an influence such as that shown in (b3) of FIG. 22, the actual image shown in (c1) of FIG. 23 is obtained, based on which a visual image, such as that shown in (c2) of FIG. 23, is obtained. That is, in a conventional example, there is a problem in that vertical lines, such as those shown in (c2) of FIG. 23, are visually recognized by a viewer.
Moreover, in the case of column reverse driving of a conventional example, a voltage range of K+ to K− is required for the source line voltage, and the maximum value of the display signal voltage is equal to or substantially equal to the non-display signal voltage. Therefore, for example, when SQ1 changes from K+ to K− in the period T01 in FIG. 20, or when SQ1 changes from K− to R+ between the periods T01 and T02, an output capability (i.e., slew rate) which is sufficiently great to support short cycles of SP1 and SP2 is required. For this reason, in a conventional case, the charging capability of the source line, i.e., the pixel writing capability, is insufficient sometimes, thereby causing degradation of the display quality of an image.
Stated otherwise, conventionally, an extremely high-cost source driver is required.
Furthermore, a reverse transition in liquid crystal cells of R, G, and B must be prevented with one type of non-display signal for CR driving, and thus there is a limit to the improvement in display quality.
In particular, because recent liquid crystal panels are increased in size and have higher definition, the number of source lines and the number of pixels are increased and stray capacitances are increased because the source line and the pixel become closer to each other. Thus, there is a tendency to worsen the aforementioned interference problem and to cause an insufficient charging time of pixels.
Accordingly, an object of the present invention is to provide a liquid crystal display device capable of displaying high-quality images, by solving the foregoing problems.